Complete list of publications

BOOK CHAPTERS

  1. V. Vankamamidi, M. Ottavi, F. Lombardi “Two-Dimensional Schemes for Clocking/Timing of QCA Circuits” in “Design and Test of Digital Circuits by Quantum-Dot Cellular Automata” Edts: F. Lombardi, J. Huang Artech House, Hardcover, Published November 2007 (No electronic version available)

  2. V. Vankamamidi, M. Ottavi and F. Lombardi “QCA Memory” in “Design and Test of Digital Circuits by Quantum-Dot Cellular Automata” Edts: F. Lombardi, J. Huang Artech House, Hardcover, Published November 2007 (No electronic version available)

  3. V. Vankamamidi, M. Ottavi, J. Huang, M. Momenzadeh and F. Lombardi “Implementing Universal Logic in QCA” in “Design and Test of Digital Circuits by Quantum-Dot Cellular Automata” Edts: F. Lombardi, J. Huang Artech House, Hardcover, Published November 2007 (No electronic version available)

  4. J. Huang, M. Momenzadeh, L.Schiano, M. Ottavi, and F. Lombardi “Tile-Based QCA Design” in “Design and Test of Digital Circuits by Quantum-Dot Cellular Automata” Edts: F. Lombardi, J. Huang Artech House, Hardcover, Published November 2007 (No electronic version available)

  5. S. Bhanja, M. Ottavi, S. Pontarelli, and F. Lombardi “QCA Circuits for Robust Coplanar Crossing” in “Emerging Nanotechnologies Test, Defect Tolerance, and Reliability” Series: Frontiers in Electronic Testing , Vol. 37 Ed. M. Tehranipoor (No electronic version available)

  6. S. Teofili, E. Nobile, S. Pontarelli, G. Bianchi “IDS Rules adaptation for packets pre-filtering in gbps line rates” in “Trustworthy Internet”, Eds. Luca Salgarelli, Giuseppe Bianchi, Nicola Blefari-Melazzi, Springer, ISBN 978-88-470-1817-4. pdf

ARCHIVAL JOURNAL PUBLICATIONS

  1. P. Reviriego, S. Pontarelli, A. Evans, J. A. Maestro, “A Class of SEC-DED-DAEC Codes Derived From Orthogonal Latin Square Codes”, accepted for publication on IEEE Transactions on Very Large Scale Integration (VLSI) Systems pdf

  2. P. Reviriego, J. Martinez, S. Pontarelli, J.A. Maestro, “A Method to Design SEC-DED-DAEC Codes With Optimized Decoding”, IEEE Transactions on Device and Materials Reliability, vol.14, no. 3, Sep. 2014. pdf

  3. P. Reviriego, S. Pontarelli, A. Sánchez-Macián, J. A. Maestro, “A Method to Extend Orthogonal Latin Square Codes”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 7, July 2014. pdf

  4. K. Namba, S. Pontarelli, M. Ottavi, F. Lombardi, “A single-bit and double-adjacent error correcting parallel decoder for multiple-bit error correcting BCH codes”, IEEE Transactions on Device and Materials Reliability, vol.14, no. 2, June 2014. pdf

  5. S. Pontarelli, P. Reviriego, J.A. Maestro, M. Ottavi, “Low Delay Single Symbol Error Correction Codes based on Reed Solomon Codes”, accepted for publication on IEEE Transactions on Computers pdf

  6. P. Reviriego, S. Pontarelli, J.A. Maestro, M. Ottavi, “A Method to Construct Low Delay Single Error Correction Codes for Protecting Data Bits Only”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on vol. 32, no.3, pp. 479-483, 2013. pdf

  7. S. Pontarelli, P. Reviriego, C. Bleakley, J. Maestro, “Low Complexity Concurrent Error Detection for Complex Multiplication”, accepted for publication on IEEE Transactions on Computers pdf

  8. P. Reviriego, S. Pontarelli, J.A. Maestro, M Ottavi, “Low-cost single error correction multiple adjacent error correction codes”, Electronics letters vol. 48 no. 23, pp. 1470-1472, 2012 pdf

  9. P. Reviriego, S. Pontarelli, C. Bleakley, J.A. Maestro, “Area efficient concurrent error detection and correction for parallel filters”, Electronics letters vol. 48 no. 20, pp. 1258-1260, 2012 pdf

  10. S. Pontarelli, G. Bianchi, S. Teofili, “Traffic-aware Design of a High Speed FPGA Network Intrusion Detection System”, accepted for publication on IEEE Transactions on Computers pdf

  11. S. Pontarelli, M. Ottavi, “Error Detection and Correction in Content Addressable Memories by Using Bloom Filters”, IEEE Transactions on Computers, vol. 62, no. 6, pp. 1111-1126, June 2013 pdf

  12. S. Pontarelli A. Salsano, “On the use of Karatsuba formula to detect errors in $GF((2^n)^2)$ multipliers”, IET Circuits, Devices & Systems, January 2012 pdf

  13. M. Ottavi, S. Pontarelli, E.P. DeBenedictis, A. Salsano, S. Murphy, P. Kogge, F. Lombardi “Partially reversible pipelined QCA circuits: combining low power with high throughput”, IEEE transactions on nanotechnology vol. 10, no 6, pp. 1383-1393, 2011 pdf

  14. S. Pontarelli, G.C. Cardarilli, M. Re, A. Salsano, “Optimized implementation of RNS FIR Filters based on FPGAs”, Journal of Signal Processing Systems, pp. 1-12, September 2010 pdf

  15. F. Karim, M. Ottavi, H. Hashempour, V. Vankamamidi, Konrad Walus, André Ivanov, F. Lombardi, ” Modeling and Evaluating Errors Due to Random Clock Shifts in Quantum-Dot Cellular Automata Circuits ”, Journal of Electronic Testing: Theory and Applications (JETTA) Volume 25 , Issue 1, Pages: 55 - 66 February 2009. pdf

  16. S. Pontarelli, M. Ottavi, V. Vankamamidi, G. Cardarilli, F. Lombardi, A. Salsano “Analysis and Evaluations of Reliability of Reconfigurable FPGAs”, Journal of Electronic Testing: Theory and Applications (JETTA) Volume 24 , Issue 1-3, Pages: 105 - 116 June 2008 pdf

  17. V. Vankamamidi, M. Ottavi, F. Lombardi, “Two-Dimensional Schemes for Clocking/Timing of QCA Circuits” IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems, Volume 27, Issue 1, Pages: 34-44, Jan. 2008. pdf

  18. G. Cardarilli, S. Pontarelli, M. Re, A. Salsano “Concurrent error detection in Reed-Solomon encoders and decoders” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 15 , Issue 7, July 2007 pdf

  19. M. Violante, L. Sterpone, A. Manuzzato, S. Gerardin, P. Rech, M. Bagatin, A. Paccagnella, C. Andreani, G. Gorini, A. Pietropaolo, G. Cardarilli, S. Pontarelli, C. Frost, “A New Hardware/Software Platform and a New 1/E Neutron Source for Soft Error Studies: Testing FPGAs at the ISIS Facility”, IEEE Transactions on Nuclear Science, Volume 54 , Issue 4, Part 2, 2007. pdf

  20. G. Cardarilli, S. Pontarelli, M. Re, A. Salsano “Analysis of Errors and Erasures in Parity Sharing RS Codecs” in IEEE Transactions on Computers, Volume 56, Issue 12, 2007 pdf

  21. V. Vankamamidi, M. Ottavi, F. Lombardi “A Serial Memory by Quantum-Dot Cellular Automata (QCA)” in IEEE Transactions on Computers, 26 Sept 2007. pdf

  22. S. Bhanja, M. Ottavi, S. Pontarelli, F. Lombardi “QCA Circuits for Robust Coplanar Crossing” in Journal of Electronic Testing: Theory and Applications (JETTA) Special Issue on Test, Defect Tolerance, and Reliability of Nanoscale Devices Volume 23 , Issue 2-3 June 2007 pdf

  23. M. Ottavi, L. Schiano, D. Tougaw, F. Lombardi “HDLQ: A HDL Environment for QCA Design” in ACM Journal on Emerging Technologies in Computing Systems (JETC) Volume 2 , Issue 4 , October 2006 pdf

  24. E.P. DeBenedictis, M.P. Frank, M. Ottavi and S.E. Frost-Murphy “On the design of reversible QDCA systems” SANDIA NATIONAL LABORATORIES TECH REPORT (2006) pdf

  25. M. Ottavi, X. Wang, L. Schiano, F.J. Meyer, Y.B. Kim, F. Lombardi, “Evaluating the Yield of Repairable SRAMS for ATE” in IEEE Transactions on Instrumentation and Measurements October 2006 pdf

  26. M. Ottavi, S. Pontarelli, V. Vankamamidi, F. Lombardi “A QCA Memory with Parallel Read/Serial Write: Design and Analysis” in IEE Proceedings Circuits, Devices and Systems vol. 153, n. 3, pp:199 - 206, June 2006 pdf

  27. G.C. Cardarilli, M. Ottavi, S. Pontarelli, M. Re, A. Salsano, “Fault Localization, Error Correction and Graceful Degradation in Signed Digit Based Adders” IEEE Transactions on Computers, vol. 55, n 5, pp :534 - 540 May 2006. pdf

  28. V. Vankamamidi, M. Ottavi, F. Lombardi. “A Line-Based Parallel Memory for QCA Implementation” in IEEE Transactions on Nanotechnology, vol. 4, n 6, pp: 690 – 698, November 2005 pdf

  29. J. Huang, M. Momenzadeh, L. Schiano, M. Ottavi, and F. Lombardi “Tile-Based QCA Design Using Majority-Like Logic Primitives” in ACM Journal on Emerging Technologies in Computing Systems (JETC) Volume 1 , Issue 3 pp: 163 - 185 October 2005 pdf

  30. G.C. Cardarilli, M. Ottavi, S. Pontarelli, M. Re, A. Salsano, “A Fault-Tolerant Solid State Mass Memory for Space Applications” in IEEE Transactions on Aerospace and Electronic Systems, vol. 41, n. 4, pp: 1353-1372, October 2005 pdf

  31. X. Wang, M. Ottavi, F. J. Meyer, F. Lombardi “Estimating the Manufacturing Yield of Compiler-based Embedded SRAMs” in IEEE Transactions on Semiconductors Manufacturing, vol. 18, n 3, pp: 412 – 421, August. 2005 pdf

  32. G.C. Cardarilli, F. Lombardi, M. Ottavi, S. Pontarelli, M. Re, A. Salsano, “Comparative Evaluation of Designs for Reliable Memory Systems” in Journal of Electronic Testing: Theory and Applications, special issue “On-line Testing and Fault Tolerance”, vol. 21, n. 4, pp. 429 – 444, August 2005 pdf

  33. G.C. Cardarilli, A. Leandri, P. Marinucci, M. Ottavi, S. Pontarelli, M. Re, A. Salsano, “Design of a Fault Tolerant Solid State Mass Memory”, IEEE Transactions on Reliability, vol. 52, n. 4, pp. 476-491, December 2003 pdf

  34. S. Bertazzoni, G.C. Cardarilli, D. Di Giovenale, M. Ottavi, S. Pontarelli, A. Salsano, P. Marinucci, “Fault Tolerant Electronic Systems for Space Applications” (Italian: Sistemi elettronici tolleranti ai guasti per applicazioni spaziali), Alta Frequenza Rivista di Elettronica, vol. 13, n. 3, June 2001. pdf

REFEREED CONFERENCE ARTICLES

  1. S. Pontarelli, M. Ottavi, A. Evans, S.J. Wen, “Error detection in Ternary CAMs using Bloom Filters”, In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013 (pp. 1474-1479) pdf

  2. Y. Lu, F. Lombardi, S. Pontarelli, M. Ottavi, “On the design of two single event tolerant slave latches for scan delay testing”, Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2012 pdf

  3. C. Bolchini, et al, “High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies”, Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2012 pdf

  4. N. Rajderkar, M. Ottavi, S. Pontarelli, J. Han, F. Lombardi, “On the Effects of Intra-gate Resistive Open Defects in Gates at Nanoscaled CMOS”, Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2011.pdf

  5. G.C. Cardarilli, L. Di Nunzio, R. Fazzolari, S. Pontarelli, M. Re, A. Salsano, “Implementation of the AES algorithm using a Reconfigurable Functional Unit”, IEEE International Symposium on Signals, Circuits and Systems (ISSCS), 2011. pdf

  6. S. Pontarelli, M. Ottavi, A. Salsano, K. Zarrineh, “Feedback based droop mitigation”, IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011 pdf

  7. S. Pontarelli, S. Teofili, “Anti-evasion Technique for Packet Based Pre-filtering for Network Intrusion Detection Systems”, Traffic Monitoring and Analysis, TMA 2011 pdf

  8. S. Pontarelli, S. Teofili, G. Bianchi “Hardware-Based “on-the-fly” Per-flow Scan Detector Pre-filter”, Traffic Monitoring and Analysis TMA 2011 pdf

  9. M. Ottavi, S. Pontarelli, A. Salsano, F. Lombardi “Modeling Magnetic Quantum-Dot Cellular Automata by HDL” IEEE Conference on Nanotechnology, IEEE-NANO 2011 pdf

  10. S. Teofili, E. Nobile, S. Pontarelli, G. Bianchi “Snort pre-filter for data-reduced intrusion detection: hardware design issues and trade-offs”, International Tyrrhenian Workshop on Digital Communications (ITWDC'10), Ponza, Italy, September 6-8, 2010.

  11. A. N. Hariharan, S. Pontarelli, M. Ottavi, F. Lombardi, “Modeling Open Defects in Nanometric Scale CMOS”, Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'10), October 2010 pdf

  12. S. Pontarelli, M. Ottavi, A. Salsano, “Error Detection and Correction in Content Addressable Memories”, Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'10), October 2010 pdf

  13. S. Pontarelli, C. Greco, E. Nobile, S. Teofili, G. Bianchi “Exploiting FPGA Dynamic Reconfiguration for Hardware based Network Intrusion Detection Systems”, 20th International Conference on Field Programmable Logic and Applications (FPL'10), Milano, ITALY pdf

  14. M. Ottavi, S. Pontarelli, E. De Benedictis, A. Salsano, P. Kogge, F. Lombardi, “High Throughput and Low Power Dissipation in QCA Pipelines using Bennett Clocking”, Proceedings of the 6th IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2010) pdf

  15. C. Greco, E. Nobile, S. Pontarelli, S. Teofili, “An FPGA based architecture for Stateful inspection of multiple TCP connections”, Proceedings of the 6th IEEE Southern Programmable Logic Conference (SPL 2010) pdf

  16. S. Pontarelli, G.C. Cardarilli, M. Re, A. Salsano,”Error correction codes for SEU and SEFI tolerant memory systems”, Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'09), October 2009 pdf

  17. S. Pontarelli, G.C. Cardarilli, M. Re, A. Salsano, “Error detection in addition chain based ECC point multiplication”, Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), June 2009. pdf

  18. G.C. Cardarilli, M. Re, A. Salsano, S. Pontarelli, “Optimization of RNS Fir Filters for 6-Inputs Lut Based FPGAs” 16th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC 2008), October 2008 pdf

  19. S. Pontarelli, G.C. Cardarilli, M. Re, A. Salsano, “A Novel Error Detection And Correction Technique for RNS based FIR Filter”, Proceedings of the The 23nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'08), October 2008 pdf

  20. S. Pontarelli, G.C. Cardarilli, M. Re, A. Salsano “On the use of Signed Digit Arithmetic for the new 6-Inputs LUT based FPGAs”, 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2008), Malta, 31 Aug.- 3 Sep. 2008 pdf

  21. S. Pontarelli, G.C. Cardarilli, M. Re, A. Salsano “Totally fault tolerant RNS based FIR filter”, Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), July 2008. pdf

  22. M. Ottavi, H. Hashempuour, F. Karim, V. Vankamamidi, K. Walus, A. Ivanov “On the Error Effects of Random Clock Shifts in Quantum-dot Cellular Automata Circuits” in Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2007, pp. 487-498, September 2007 pdf

  23. S. Pontarelli, L. Sterpone, G.C. Cardarilli, M. Re, M. Sonza Reorda, A. Salsano, M. Violante “Optimization of Self Checking FIR filters by means of Fault Injection Analysis”, Proceedings of the The 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07), September 2007 pdf

  24. S. Pontarelli, L. Sterpone, G.C. Cardarilli, M. Re, M. Sonza Reorda, A. Salsano, M. Violante “Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders”, Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), July 2007. pdf

  25. M. Violante, M. Sonza Reorda, L. Sterpone, A. Manuzzato, S. Gerardin, P. Rech, M. Bagatin, A. Paccagnella, C. Andreani, G. Gorini, A. Pietropaolo, G. Cardarilli, A. Salsano, S. Pontarelli, C. Frost, “A new hardware/software platform for the soft-error sensitivity evaluation of FPGA devices”, IEEE Latin-America Test Workshop 2007, Cuzco, Perù

  26. M. Violante, L. Sterpone, A. Manuzzato, S. Gerardin, P. Rech, M. Bagatin, A. Paccagnella, C. Andreani, A. Pietropaolo, G. Cardarilli, S. Pontarelli, C. Frost, “A new hardware/software platform and a new 1/E neutron source for soft error studies: testing FPGAs at the ISIS facility” 2006 Radiation Effects on Components and Systems Workshop.

  27. S. Pontarelli, M. Ottavi, V. Vankamamidi, A. Salsano, F. Lombardi “Reliability Evaluation of Repairable/Reconfigurable FPGA” in Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2006, October 2006 pdf

  28. M. Ottavi, S. Pontarelli, A. Leandri, A. Salsano “Design and Evaluation of an Hardware on-line Program-Flow Checker for Embedded Microcontrollers” in Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2006, October 2006 pdf

  29. V. Vankamamidi M. Ottavi and F. Lombardi “Clocking and Cell Placement for QCA” in IEEE-Nano2006, pp. 343- 346, June 2006 pdf

  30. M. Ottavi, L. Schiano, S. Pontarelli, V. Vankamamidi, F. Lombardi “Timing Verification of QCA Memory Architectures” in IEEE-Nano2006, June 2006. pdf

  31. G.C. Cardarilli, M. Ottavi, S. Pontarelli, M.Re, A. Salsano “Localization of faults in Radix-n Signed Digit Adders” in IEEE International On-Line Testing Symposium (IOLTS 2006)pdf

  32. G.C. Cardarilli, S. Pontarelli, M. Re, A. Salsano, “Concurrent Error Detection in Reed Solomon Decoders”, IEEE International Symposium on Circuits and Systems ISCAS 2006, Kos, Greece, May 2006. pdf

  33. G.C. Cardarilli, S. Pontarelli , M. Re, A. Salsano, “Fault Tolerant Design of Signed Digit Based Filters”, IEEE International Symposium on Circuits and Systems ISCAS 2006, Kos, Greece, May 2006. pdf

  34. S. Bhanja, M. Ottavi, S. Pontarelli, F. Lombardi, “Novel Designs for Thermally Robust Coplanar Crossing in QCA” in Proceedings of IEEE Design and Testing in Europe, March 2006 pdf

  35. M. Momenzadeh, M. Ottavi, F. Lombardi “Modeling QCA Defects at Molecular-level in Combinational Circuits” in Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems DFT 2005, Monterey, California, October 2005 pdf

  36. G.C. Cardarilli, S. Pontarelli , M. Re, A. Salsano, “A Self Checking Reed Solomon Encoder: Design and Analysis”, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2005, Monterey, CA, USA., October 2005 pdf

  37. G.C. Cardarilli, S. Pontarelli , M. Re, A. Salsano, “FPGA oriented design of parity sharing RS codecs ”, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2005, Monterey, CA, USA., October 2005. pdf

  38. M. Ottavi, S. Pontarelli, V. Vankamamidi, F. Lombardi “Novel approaches to QCA memory design” in Proceedings of 5th IEEE Conference on Nanotechnology IEEE-NANO 2005, Nagoya, July 2005pdf

  39. M. Ottavi, S. Pontarelli, V. Vankamamidi, A. Salsano, F. Lombardi “Design of a QCA Memory with Parallel Read/Serial Write” in Proceedings of 2005 IEEE Computer Society Annual Symposium on VLSI Tampa, Florida, May 2005 pdf

  40. M. Ottavi, S. Pontarelli, L. Schiano, G.C. Cardarilli, F. Lombardi “Evaluating Data Integrity of Memory Systems by Configurable Markov Models” in Proceedings of 2005 IEEE Computer Society Annual Symposium on VLSI Tampa, Florida, May 2005 pdf

  41. V. Vankamamidi, M. Ottavi, F. Lombardi “Tile Based Design of a Serial Memory in QCA” in Proceedings of ACM Great Lakes Symposium on VLSI Chicago, Illinois, Apr. 2005.

  42. L. Schiano, M. Ottavi, F. Lombardi, S. Pontarelli, A. Salsano, “On the Analysis of Reed Solomon Coding for Resilience to Transient/Permanent Faults in Highly Reliable Memories” in Proceedings of IEEE Design and Testing in Europe, Munich, Germany, Mar. 2005. pdf

  43. X. Wang, M. Ottavi, F. Meyer, F. Lombardi, “On The Yield of Compiler-based eSRAMs”, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2004, Cannes, France, October 2004. pdf

  44. X. Wang, M. Ottavi, F. Lombardi, “Testing of Inter – Word Coupling Faults in Word-Oriented SRAMs.”, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2004 , Cannes, France, pp. Pages:111 – 119, October 2004. pdf

  45. G. Cardarilli, M. Ottavi, S. Pontarelli , M. Re, A. Salsano, “Data Integrity Evaluations of Reed Solomon Codes for Storage Systems”, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2004, Cannes, France, pp. 158 – 164, October 2004. pdf

  46. L. Schiano, M. Ottavi, F. Lombardi, “Markov Models of Fault-Tolerant Memory Systems under SEU ”, IEEE International Workshop on Memory Technology, Design and Testing, San Jose' CA, pp. 38 – 43, August 2004. pdf

  47. G.C. Cardarilli, M. Ottavi, S. Pontarelli, M. Re, A. Salsano, “A Signed Digit Adder with Error Correction and Graceful Degradation Capabilities”, Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), Funchal, Madeira Island, Portugal, pp. 141 – 146, July 2004. pdf

  48. G. Cardarilli, M. Ottavi, S. Pontarelli , M. Re, A. Salsano, “A Fault-Tolerant Solid State Mass Memory for Highly Reliable Instrumentation”, IEEE Instrumentation and Measurement Technology Conference, Como, Italy, pp 1651 - 1656 Vol.3 May 2004. pdf

  49. M. Ottavi, L. Schiano, X. Wang, Y.B. Kim, F. Meyer, F. Lombardi, “Yield Evaluation Methods of SRAM Arrays: a Comparative Study”, IEEE Instrumentation and Measurement Technology Conference, Como, Italy, pp. 1525 – 1530 Vol.2, May 2004. pdf

  50. M. Ottavi, X. Wang, F.J. Meyer, F. Lombardi, “Simulation of Reconfigurable Memory Core Yield”, ACM Great Lakes Symposium on VLSI 2004, Boston, MA , pp. 136 – 140, April 2004. pdf

  51. X. Wang, M. Ottavi, F. Lombardi, “Yield Analysis of Compiler – based Arrays of Embedded sRAMs”, The 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Cambridge, MA U.S.A., pp. 3 – 10, November 2003. pdf

  52. G.C. Cardarilli, M. Ottavi, S. Pontarelli, M. Re, A. Salsano, “Error Detection in Signed Digit Arithmetic Circuit with Parity Checker”, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2003, Cambridge, MA, USA, pp. 401 – 408, November 2003.pdf

  53. G.C. Cardarilli, M. Ottavi, S. Pontarelli , M. Re, A. Salsano, “A Fault Tolerant Hardware Based File System Manager for Solid State Mass Memory”, 2003 IEEE International Symposium on Circuits and Systems, Bangkok, Thailand, pp.V – 649 – V – 652 vol.5, May 2003. pdf

  54. G.C. Cardarilli, F. Kaddour, A. Leandri, M. Ottavi, S. Pontarelli, R. Velazco, “Bit flip injection in processor – based architectures: a case study”, 8th IEEE International On – Line Testing Workshop, IOLTW , Hotel Delos – Isle of Bendor, France , pp. 117 – 127 July 2002. pdf

  55. S. Pontarelli, G.C. Cardarilli, A. Leandri, M. Ottavi, M. Re, A. Salsano, “A Self – Checking Cell Logic Block for Fault Tolerant FPGAs ”, ISCAS 2002, Scottsdale, Arizona, USA, pp. IV – 477 – IV – 480 vol.4, May 2002. pdf

  56. S. Pontarelli, G.C. Cardarilli, A. Malvoni, M. Ottavi, M. Re, A. Salsano, “System – on – Chip Oriented Fault – Tolerant Sequential Systems Implementation Methodology”, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2001, San Francisco, California, USA , pp. 455 – 460, October 2001. pdf

  57. M. Ottavi, G.C. Cardarilli, D. Cellitti, S. Pontarelli, M. Re, A. Salsano, “Design of a Totally Self Checking Signature Analysis Checker for Finite State Machines”, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2001, San Francisco, California, USA, pp. 403 – 411 October 2001. pdf

  58. M. Ottavi, G.C. Cardarilli, P. Marinucci, S. Pontarelli, M. Re, A. Salsano, “Development of a dynamic routing system for a fault tolerant solid state mass memory”, IEEE International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, pp. 830 – 833 vol. 4, May 2001. pdf

  59. G.C. Cardarilli, P. Marinucci, M. Ottavi, A. Salsano, “A Fault – tolerant 176 Gbit Solid State Mass Memory Architecture”, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2000, Yamanashi, Japan, pp. 173 – 180, October 2000. pdf




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