Collaborations:

  • Prof. Fabrizio Lombardi, Northeastern University, Boston (MA) USA (Home Page)
  • Prof. Juan Antonio Maestro and Prof. Pedro Reviriego Vasallo, Universidad Antonio de Nebrija, Madrid, Spain (Home page)
  • Networking Group, University of Rome “Tor Vergata”, Rome, ITALY (NetGroup)
  • Dr. Alessandro Marchioro, Micro Electronics section at CERN, Geneve Switzerland (Home page)
  • Prof. Sanjukta Bhanja, University of South Florida, Tampa (FL) USA (Home page)
  • Prof Konrad Walus, University of British Columbia, Vancouver (BC) Canada (Home page)
  • Dr. Erik DeBenedictis, Sandia National Laboratories, Albuquerque (NM) USA (Home page)
  • Prof Alessandro Paccagnella, University of Padova, Padova, ITALY (RREACT Group)
  • Dr. Gianluca Furano, and Dr. Marco Rovatti European Space Agency, The Hague Area, Netherlands, Data System Division
  • NEAT Embedded Computing S.r.l. Rome (NEAT)

Conferences

  • The Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN) (MEDIAN)
  • The IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS)
  • The 4th Workshop on Design for Reliability (DFR 2012) (DFR12)

Code Repository

  • Verilog source codes for fast Single Error Correction (SEC) code. The paper describing the SEC code is here.
  • Verilog source codes for HDLQ. The paper describing the HDLQ code is here.

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