Marco Ottavi


Associate Professor
University of Rome “Tor Vergata”
Department of Electronic Engineering

Tel (+39) 06 7259 7344
FAX (+39) 06 233222594
e-mail: ottavi AT ing.uniroma2.it


Marco Ottavi is currently an Associate Professor at the University of Rome Tor Vergata, before he was a Research Professor with the same University as the recipient of a “rientro dei cervelli” fellowship awarded by the Italian Ministry of University and Research. He previously worked as a Senior Design Engineer at AMD and held post doc positions with Sandia National Laboratories and with the Department of Electrical and Computer Engineering of Northeastern University in Boston. He received the Ph.D. in Microelectronics and Telecommunications Engineering from University of Rome “Tor Vergata” and the Laurea degree in Electronic Engineering from University of Rome “La Sapienza”. His research interests include yield and reliability modeling, fault-tolerant architectures, on-line testing and design of nano scale circuits and systems. From December 2011 to November 2015 he has been the Chair of COST Action IC1103 “Manufacturable and Dependable Multicore Architectures at Nanoscale” (MEDIAN). He is a Senior Member of the IEEE.



RESEARCH INTERESTS

  • Reliability Modeling and Enhancement
  • Fault-Tolerant Design Techniques
  • VLSI Design and Design for Testability
  • Nanotechnology and Emerging Hardware paradigms for Computing (QCA, Resistive devices)
  • Reconfigurable Devices and Computing
  • Computer Architecture
  • Manufacturing Yield Characterization



AFFILIATIONS AND PROFESSIONAL ACTIVITIES

(2015) Track chair of “International Conference on Design & Technology of Integrated Systems in Nanoscale Era” (DTIS 2015)

(2014) General co-chair of the “Joint MEDIAN–TRUDEVICE Open Forum”

(2014) General co-chair of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT14)

(2013) Co-organizer of the “First International School on Manufacturable and Dependable Multicore Architectures at nanoscale” Rome September 2013

(2013) Program co-chair of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT13)

(2012) Guest Editor of IEEE Transactions on Nanotechnology, Special Section “Defect & Fault Tolerance in VLSI and Nanotechnology Systems”

(2012) Co-organizer of the HiPEAC Computing Systems Week Special Session “The intertwining challenges of reliability, testing and verification”

(2012 – Present) Member of the Technical Program Committee of track D6 “Emerging Technologies, Systems and Applications” of DATE (Design Automation & Test in Europe) 2013

(2012) Member of Program Committee of IEEE/ACM Symposium On Nanoscale Architectures Nanoarch'12

(2012)Member of Technical Program Committee of the IEEE International On-Line Testing Symposium (IOLTS 2012)

(2012 – Present) Served as grant proposals reviewer for the following organizations:

  • Israel Science Foundation,
  • European Union COST Office

(2011 – Present) Chair of the COST Action IC1103 “Manufacturable and Dependable Architectures at Nanoscale”

(2011 –2013) Member of the Editorial Board of ISRN Electronics

(2010 – Present) Senior Member of the IEEE

(2012) Member of Technical program Committee of the 4th Workshop on Design for Reliability (DFR 2012)

(2011 – Present) Member of Technical program Committee of the IEEE International On-Line Testing Symposium

(2010) Publicity chair of the 6th IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH ‘10)

(2006 –2009) Publicity chair of the 21st, 22nd, 23rd, and 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'06 DFT’07 DFT’08 DFT’09)

(2009) Member of program Committee of GLSVLSI 2009

(2008-2009) Member of program Committee of the IEEE North Atlantic Test Workshop

(2008) Chair of the session “Dependability Analysis and Evaluation” at the 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'08)

(2007) Chair of the session “Emerging technologies” at the 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07)

(2007) Member of program Committee of IEEE/ACM Symposium On Nanoscale Architectures Nanoarch'07

(2006 –Present) Member of the Program Committee of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

(2006) Chair of the session “Fault Tolerant Designs” at the 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'06)

(2004 –2006) Member of Test and Reliability Group, Northeastern University

(2003 – Present) Served as reviewer for the following journals and peer reviewed conferences:

  • IEEE Design and Test Magazine,
  • IEEE Transactions on VLSI Systems,
  • IEEE Transactions on Computers,
  • IEEE Transactions on Reliability,
  • IEEE Transactions on Nanotechnology,
  • IEEE Systems Journal,
  • ACM Journal on Emerging Technologies in Computing Systems
  • Springer Applied Nanosciences
  • Design and Automation Conference (DAC)
  • International Test Conference (ITC)
  • IEEE International Symposium on Defect and Fault Tolerance
  • IEEE International On-Line Testing Symposium
  • IEEE North Atlantic Test Workshop

(2003 -2010) Member of The IEEE (Institute of Electrical and Electronics Engineers)

(2001 – 2011) Member of Gruppo Elettronica – GE (The Italian Group of Electronics)

(2000 – 2004) Member of Microelectronics Lab Research Group, University of Rome “Tor Vergata”

(2000 –Present) Attended and given presentations at several IEEE Sponsored Meetings.


AWARDS and HONORS

(2010) Elevated to Senior Member of IEEE

(2009) Recipient of a “rientro dei cervelli” (reverse brain drain) fellowship awarded by the Italian Ministry of University and Research

(2008) Included in “Who’s who in America”

(2007) Approved for an “Outstanding Researcher” or EB1 visa by the United States National Visa Center.

(2006) Nomination for IEEE Test Technology Technical Council (TTTC) Service Awards


PUBLICATIONS

A partial list of my publications which includes some bibliographic metrics can be found here


TEACHING

Affidabilità di Componenti e Sistemi VLSI
Fondamenti di Elettronica: Elettronica Digitale
Available Theses - Argomenti per Tesi di Laurea Magistrale (page in Italian).

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