Welcome to the homepage of the Defect and Fault Tolerance group at the University of Rome "Tor Vergata"

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News 15 May 2012
old news

Two papers of our group have been recently accepted for publication of IEEE Transaction on Computers (Selected list of publications)












Our research interests are design for test, yield and reliability modeling, fault-tolerant architectures, on-line testing, error correcting codes. In close collaboration with the DSP VLSI Group, we have an established expertise in the design of advanced testing architectures, reliable systems for space applications, and nano scale circuits and systems.

Available Theses - Argomenti per Tesi di Laurea Magistrale (page in Italian).

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