Defect and Fault Tolerance Group

Sono disponibili tesi su diversi argomenti inerenti l'attività di ricerca del gruppo. Gli studenti interessati possono contattare il Prof. Marco Ottavi o il Dott. Salvatore Pontarelli.

RISC-V è una architettura Reduced Instruction Set sta che sta risvegliando molto interesse per la sua caratteristica di essere aperta e disponibile a tutti gli sviluppatori. Il codice sorgente RISC-V è disponibile in varie versioni inclusa una che può essere implementata su FPGA. Le tesi proposte richiedono di studiare l'architettura del processore e di sviluppare apposite tecniche di tolleranza ai guasti per vari elementi del processore per aumentarne l'affidabilità a fronte di guasti temporanei e/o permanenti.

1) Integrità della sicurezza funzionale (SIL): sviluppo di una soluzione con il massimo livello di SIL come kernel drivers in ambiente Linux/BSD.

2) Progettazione e sviluppo di una suite per test, debug e qualifica di piattaforme embedded.

3) Sviluppo di una nuova piattaforma per la generazione automatica di test script per sistemi di segnalamento ferroviario di ultima generazione.

4) Progettazione e sviluppo di una HMI via WEB per applicazioni critiche per la sicurezza

Nell'ambito della collaborazione scientifica con l'agenzia spaziale europea (ESA) nei Paesi Bassi sono possibili varie attività per la caratterizzazione di sistemi elettronici digitali di diversa complessità e resilienza all'interazione con fenomeni radiativi tipici dell'ambiente spaziale.

Motivazione e descrizione degli argomenti d tesi disponibili presso ESA:


Space-Grade Reference Designs using microcontrollers

We foresee that software based data acquisition/processing and simple control applications will be widely used in many spacecraft subsystems. They allow implementing software based control architectures that provide a higher flexibility and autonomous capability versus hardware implementations. For this type of applications, where limited performances are requested to the processor, general purpose microprocessors are usually considered not compatible due to high power consumption, high pin count packages, need of external memories and peripherals. Low-end microcontrollers are considered more attractive in many applications such as:

• propulsion system control
• sensor bus control
• robotics applications control
• simple motor control
• mechanism control
• power control
• particle detector instrumentation
• radiation environment monitoring
• thermal control
• antenna pointing control
• AOCS/GNC (Gyro, IMU, MTM)
• RTU control
• Simple instrument control
• Wireless networking

In these kind of applications the microcontroller device should have a relatively low price, a low power consumption, a limited number of pins and must integrate small amount of RAM and most of the I/O peripherals for control and data acquisition (serial I/Fs, GPIO’s, PWM , ADC etc.). The requirements for memory and program length are usually minimal, with no or very simple operating system and low software complexity.

The Space Avionics market was very positively influenced by the availability of IP cores (ESA or Commercial) allowing fast prototyping and design of complex systems. Company know-how, rather than being diminished was boosted by the increased productivity and the portfolio of ASSP and design increased their market competitiveness, both at prime level (TAS, ASD example) and at equipment manufacturers’ (RUAG). There is the room to apply this industrial setup to many other fields beyond IPs. The availability of ‘cheap’ distributed intelligence (in form of microcontrollers) allows for standalone design blocks for many avionics functions.

The space market has, so far, been confined to either use a full fledged microprocessor, like the LEON, or handcraft increasingly complex state machines in overly loaded FPGAs. There's no man in the middle available to system designers to offload the complexity of current designs and reuse is limited to functions that are often not posing the major design or verification challenges (memory controllers, PWMs, serial ports, …).

A microcontroller may come to the rescue though, providing a solution that fits in between the overly loaded FPGAs and the hugely complex microprocessor, providing another layer of abstraction to tackle complexity. Moreover, a microcontroller based solution may quickly respond to rapidly changing needs and securing development and verification efforts, delegating repetitive and highly parallelizable functions to the FPGAs (packet switching, low level protocols, hardware interface, interconnection,…), while keeping the algorithmic intelligence of decision making.

Use Cases that can be implemented for microcontroller-based reference designs (each one can be a separate thesis):

a. Flash Translation Layer

b. CANopen

c. Remote Terminal Unit command handler (analog acquisition, control and command)

With this list of use cases we are trying to demonstrate the flexibility and capability of such a solution in the handling of otherwise complex functions if purely implemented in hardware.

NAND Flash devices are appealing components for next generation payloads and platforms and the possibility to handle them through a soft core that can implement an abstraction layer on top of the low level hardware protocol (ONFI) is of great interest.

CANopen is a standard that is getting momentum in the space market and being able to handle the protocol through a software stack on the soft core is of increasing interest.