Research on Dependable and Secure Systems

The latest studies on this research area are related to:

Microprocessor Protection Architectures against Hardware Trojans

Software exploitable Hardware Trojan Horses (HWTs) have been currently inserted in commercial CPUs and, very recently, in memories. Such attacks may allow malicious users to run their own software or to gain unauthorized privileges over the system. Therefore, HWTs are nowadays considered a serious threat both from academy and industry. We focus on protection architectures meant to shield the communication within the CPU and between the CPU and the memory in a microprocessor-based system. The approach aims at detecting the activation on HWTs infesting microprocessor architectures.

Error Detection and Correction in Content Addressable Memory (CAM)

The CAM are SRAM based memories able to compare the input data against the data stored in the memory, providing as result the address of the matching data. A CAM is able to access within a clock cycle, to all of the entries stored in its memory table and to compare them to the provided input. CAM with small dimensions are used in cache or Translation Lookaside Buffers (TLB), while large CAM are used in systems that performs rapid search within a large amount of data. Nowadays one of the most used application of CAM are related to packet forwarding and classification in high speed network systems. In recent years the implementation of CAM with large memory has been driven by their use in network systems, that continuously increases the performance request of such components. The use of nanometric scale technologies increases the error rate due to the occurrence of Single Event Upsets for such systems. Our research is focused on design error detection and correction code able to tolerate SEU error in the CAMs.

Feedback based Droop Mitigation

A strong dI/dt event in a VLSI circuit can induce a temporary voltage drop and consequent malfunctioning of logic as for instance failing speed paths. This event, called power droop, usually manifests itself in at-speed scan test where a surge in switching activity (capture phase) follows a period of quiescent circuit state (shift phase). Power droop is also present during mission mode operation. However, because of the less predictable occurrence of the switching events in mission mode, usually the values of power droop measured during test are different from those measured in mission mode. To overcome the power droop problem, different mitigation techniques have been proposed. The goal of these techniques is to create a uniform current demand throughout the test. This work proposes a feedback based droop mitigation technique which can adapt to the droop by reading the level of VDD and modifying real time the current flowing on ad-hoc droop mitigators. The proposed solution not only can compensate for droop events occurring during test mode but also can be used as a method of mission mode droop mitigation and yield enhancement if higher power consumption is acceptable.

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