http://dftgroup.uniroma2.it/ 2026-04-10T19:12:06+02:00 http://dftgroup.uniroma2.it/ http://dftgroup.uniroma2.it/lib/images/favicon.ico text/html 2022-01-21T21:58:32+02:00 mottavi http://dftgroup.uniroma2.it/doku.php?id=people&rev=1642798712&do=diff Staff Prof. Marco Ottavi Alessandro Palumbo Former Staff Daniele Felici Dr. Vishal Gupta Alumni Laurea (B.Sc.) Dario Asciolla Elena Grosso Danilo Pellegrini Bruno Luzzi Danilo Pellegrini Carla Marzullo Federico Filogonio text/html 2021-07-22T07:03:39+02:00 mottavi http://dftgroup.uniroma2.it/doku.php?id=vishal&rev=1626930219&do=diff Vishal Gupta ---------- Postdoctoral researcher University of Rome Tor Vergata Department of Electronic Engineering ---------- Vishal Gupta is a postdoctoral researcher at the university of Rome Tor Vergata. His research interests include Device Characterization and Modeling, Design issues in Nanotechnology (Memristors, FinFET, CMOS), VLSI Design and Technology, and Design for Testability (Analog & Digital), Nanoscale Memory Design, Perovskite Solar Cells for Memory, Neuromorphic, and… text/html 2020-11-15T08:35:27+02:00 mottavi http://dftgroup.uniroma2.it/doku.php?id=research&rev=1605425727&do=diff Dependable and Secure Systems Study of the sources of error that can cause a system to behave not according to the expected functionality. Focus on both non-malicious (fault tolerance) and malicious causes (hardware security). more info... Novel Computational Paradigms at Nanoscale Study of the novel nanoscale technologies for the development of gigascale systems. Particular expertise on resistive devices such as RRAM and memristors and Field Coupled Nanocomputing such as NML and QCA . … text/html 2020-11-15T08:17:38+02:00 mottavi http://dftgroup.uniroma2.it/doku.php?id=fault&rev=1605424658&do=diff Research on Dependable and Secure Systems The latest studies on this research area are related to: Microprocessor Protection Architectures against Hardware Trojans Software exploitable Hardware Trojan Horses (HWTs) have been currently inserted in commercial CPUs and, very recently, in memories. Such attacks may allow malicious users to run their own software or to gain unauthorized privileges over the system. Therefore, HWTs are nowadays considered a serious threat both from academy and… text/html 2020-11-15T07:58:22+02:00 mottavi http://dftgroup.uniroma2.it/doku.php?id=marco&rev=1605423502&do=diff Marco Ottavi ---------- Associate Professor University of Rome “Tor Vergata” Department of Electronic Engineering Tel (+39) 06 7259 7344 FAX (+39) 06 233222594 e-mail: ottavi AT ing.uniroma2.it Marco Ottavi on ResearchGate Marco Ottavi on Linkedin text/html 2020-11-15T07:42:05+02:00 mottavi http://dftgroup.uniroma2.it/doku.php?id=palumbo&rev=1605422525&do=diff Alessandro Palumbo ---------- PhD Student University of Rome Tor Vergata Department of Electronic Engineering ---------- Alessandro Palumbo is currently a PhD student in electronic engineering. ---------- text/html 2020-07-05T09:49:20+02:00 mottavi http://dftgroup.uniroma2.it/doku.php?id=start&rev=1593935360&do=diff Our research interests are design for test, yield and reliability modeling, fault-tolerant architectures, on-line testing, error correcting codes. We have an established expertise in the design of advanced testing architectures, reliable systems for space applications, and nano scale circuits and systems. Available Theses text/html 2018-04-27T08:14:22+02:00 mottavi http://dftgroup.uniroma2.it/doku.php?id=contact&rev=1524809662&do=diff Contact e-mail ottavi AT ing.uniroma2.it Address DFT Group Università di Roma “Tor Vergata” Dipartimento di Ingegneria Elettronica Via del Politecnico, 1 00133 Roma Italy text/html 2018-04-27T08:13:37+02:00 mottavi http://dftgroup.uniroma2.it/doku.php?id=links&rev=1524809617&do=diff Collaborations: * Prof. Fabrizio Lombardi, Northeastern University, Boston (MA) USA (Home Page) * Prof. Juan Antonio Maestro and Prof. Pedro Reviriego Vasallo, Universidad Antonio de Nebrija, Madrid, Spain (Home page) * Networking Group, University of Rome “Tor Vergata”, Rome, ITALY (NetGroup) * Dr. Alessandro Marchioro, Micro Electronics section at CERN, Geneve Switzerland (Home page) * Prof. Sanjukta Bhanja, University of South Florida, Tampa (FL) USA (Home page) * Pr… text/html 2018-03-07T11:28:55+02:00 mottavi http://dftgroup.uniroma2.it/doku.php?id=thesis&rev=1520418535&do=diff Tesi disponibili Sono disponibili tesi su diversi argomenti inerenti l'attività di ricerca del gruppo. Gli studenti interessati possono contattare il Prof. Marco Ottavi o il Dott. Salvatore Pontarelli. Tecniche di tolleranza ai guasti sul processore Risc-V RISC-V è una architettura Reduced Instruction Set sta che sta risvegliando molto interesse per la sua caratteristica di essere aperta e disponibile a tutti gli sviluppatori. Il codice sorgente RISC-V è disponibile in varie versi… text/html 2017-02-04T09:42:28+02:00 mottavi http://dftgroup.uniroma2.it/doku.php?id=news&rev=1486197748&do=diff News 3 February 2017 news Special Issues of Transactions on Emerging Topics in Computing. “Advanced Command, Control and On-Board Data Processing for Space Avionic Systems” Submission deadline: September 1, 2017. News 3 February 2017 news Special Issues of Transactions on Emerging Topics in Computing. “Design of Reversible Computing Systems Submission deadline: March 1, 2018. News 3 February 2017 news Congratulations to the Nemesys team for being admitted to fly their experiment in the … text/html 2015-04-11T12:09:44+02:00 sal http://dftgroup.uniroma2.it/doku.php?id=complete&rev=1428746984&do=diff BOOK CHAPTERS * V. Vankamamidi, M. Ottavi, F. Lombardi “Two-Dimensional Schemes for Clocking/Timing of QCA Circuits” in “Design and Test of Digital Circuits by Quantum-Dot Cellular Automata” Edts: F. Lombardi, J. Huang Artech House, Hardcover, Published November 2007 (No electronic version available) * V. Vankamamidi, M. Ottavi and F. Lombardi “QCA Memory” in “Design and Test of Digital Circuits by Quantum-Dot Cellular Automata” Edts: F. Lombardi, J. Huang Artech House, Hardcover, Publish… text/html 2015-04-03T10:35:24+02:00 mottavi http://dftgroup.uniroma2.it/doku.php?id=salsano&rev=1428050124&do=diff In Memoriam: Prof. Adelio Salsano Il Prof. Adelio Salsano era nato il 26 Dicembre 1941. Laureatosi con lode in Ingegneria Elettronica, ha conseguito la libera docenza. Ha assunto inizialmente il ruolo di tecnico, poi quello di assistente ed infine di professore associato presso l’Università degli Studi di Roma La Sapienza. Passato nel 1981 all’Università degli Studi di Roma Tor Vergata, ha ricoperto il ruolo di professore ordinario di microelettronica. Ha svolto anche un’intensa attività … text/html 2015-03-24T14:41:43+02:00 sal http://dftgroup.uniroma2.it/doku.php?id=publications&rev=1427204503&do=diff P. Reviriego, S. Pontarelli, J.A. Maestro, M. Ottavi, “A Method to Construct Low Delay Single Error Correction Codes for Protecting Data Bits Only”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on vol. 32, no.3, pp. 479-483, 2013. [pdf] text/html 2011-11-17T09:36:32+02:00 sal http://dftgroup.uniroma2.it/doku.php?id=sal&rev=1321518992&do=diff Salvatore Pontarelli ---------- Post Doc University of Rome “Tor Vergata” Department of Electronic Engineering tel. (+39) 06 7259 7811 FAX (+39) 06 233222594 e-mail: pontarelli AT ing.uniroma2.it ---------- Salvatore Pontarelli is currently postdoctoral research associate at the University of Rome, Tor Vergata. He received the Laurea degree in Electronic Engineering from the University of Bologna in 1999 and the Ph.D. in Microelectronics and Telecommunications Engineering fro… text/html 2011-05-04T12:00:27+02:00 mottavi http://dftgroup.uniroma2.it/doku.php?id=nano&rev=1304503227&do=diff Research on Nanotechnologies The latest studies on this research area are related to: High Throughput and Low Power Dissipation in QCA Pipelines using Bennett Clocking A detailed analysis of an architectural pipeline scheme for Quantum-dot Cellular Automata (QCA) has been carried out. This scheme utilizes the so-called Bennett clocking for attaining high throughput and low power dissipation. In this arrangement, computation stages (utilizing Bennett clocking) and memory stages combine the… text/html 2011-04-23T21:50:08+02:00 sal http://dftgroup.uniroma2.it/doku.php?id=setup&rev=1303588208&do=diff Prototype Setup The setup of a prototype of the Solid State Mass Memory is shown below. The photo shown were taken at the microelectronic laboratory of Electronic Engineering Department. In photo 1 the setup of dynamic router and Spacewire interfaces is shown. The main building blocks of this setup are one plate implementing the dynamic router and two plates implementing the Spacewire/Personal Computer interfaces. In this setup the two memory modules are not shown. On the plate implem… text/html 2011-04-23T00:27:22+02:00 sal http://dftgroup.uniroma2.it/doku.php?id=ssmm&rev=1303511242&do=diff The Solid State Mass Memory The design of electronic systems for space applications must consider several problems related to the harsh environment in which the system is employed. In fact, in the space environment the electronic components are stressed by a large number of physical phenomena, like mechanical stresses, ionizing radiations and critical thermal conditions. To face these specific application constraints, the typical approach has been the development of space qualified electronic… text/html 2011-04-23T00:05:19+02:00 sal http://dftgroup.uniroma2.it/doku.php?id=iafolla&rev=1303509919&do=diff Lorenzo Iafolla ---------- Ph.D. Student University of Rome “Tor Vergata” Department of Electronic Engineering e-mail: iafolla AT ing.uniroma2.it ---------- Lorenzo Iafolla is currently a Ph.D. student at the University of Rome, Tor Vergata, in Microelectronics and Telecommunications Engineering and is a scholarship holder at the INFN (National Institute of Nuclear Physics). He received the Laurea degree in Physics from the University of Rome, Tor Vergata, in 2009. His research ma… text/html 2011-04-23T00:04:33+02:00 sal http://dftgroup.uniroma2.it/doku.php?id=felici&rev=1303509873&do=diff Daniele Felici ---------- Ph.D. Student University of Rome “Tor Vergata” Department of Electronic Engineering e-mail: felici AT ing.uniroma2.it ---------- Daniele Felici is currently a PhD student in Microelectronics and Telecommunications Engineering at the University of Rome “Tor Vergata”. He took his Master degree in Electronics Engineering at the University of Rome “La Sapienza” in 2010. His PhD focuses mainly on the radiation hardness and the fault tolerance in digital design,…