~~NOTOC~~

===== Collaborations: ===== 

    * Prof. Fabrizio Lombardi,  Northeastern University, Boston (MA) USA ([[http://www.coe.neu.edu/people/lombardi-fabrizio|Home Page]])
    * Prof. Juan Antonio Maestro and Prof. Pedro Reviriego Vasallo, Universidad Antonio de Nebrija, Madrid, Spain  ([[http://www.nebrija.es/~jmaestro/esa/members.htm|Home page]])
    * Networking Group,  University of Rome "Tor Vergata", Rome, ITALY  ([[http://netgroup.uniroma2.it/|NetGroup]])
    * Dr. Alessandro Marchioro,  Micro Electronics section at CERN, Geneve Switzerland ([[http://ph-dep-ese.web.cern.ch/ph-dep-ese/structure/me.html|Home page]]) 
    * Prof. Sanjukta Bhanja,  University of South Florida, Tampa (FL) USA  ([[http://www.eng.usf.edu/~bhanja/|Home page]])
    * Prof Konrad Walus,  University of British Columbia, Vancouver (BC) Canada ([[http://www.mina.ubc.ca/konradw|Home page]]) 
    * Dr. Erik DeBenedictis, Michael P. Frank Sandia National Laboratories, Albuquerque (NM) USA ([[http://netalive.startlogic.com/debenedictis.org/erik/|Home page]])
    * Prof Alessandro Paccagnella,  University of Padova, Padova, ITALY  ([[http://rreact.dei.unipd.it/|RREACT Group]])
    * Dr. Gianluca Furano,  and Dr. Marco Rovatti European Space Agency, The Hague Area, Netherlands, Data System Division
    *  NEAT Embedded Computing S.r.l. Rome ([[http://www.neat.it/|NEAT]]) 
    * INTECS SOLUTIONS S.p.A..  Rome ([[http://www.intecs.it/page/homepage|INTECS]]) 


===== Conferences ===== 

    * The Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN) ([[http://www.median-project.eu/median2013.htm|MEDIAN]])
    * The IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems ([[http://www.dfts.org|DFTS]])
    * The 4th Workshop on Design for Reliability (DFR 2012) ([[http://www.cs.ucy.ac.cy/carch/DFR2012/|DFR12]])

===== Code Repository ===== 

    * Verilog {{:tcad_verilog.zip|source}} codes for fast Single Error Correction (SEC) code. The paper describing the SEC code is {{:tcad13.pdf|here}}.     
    * Verilog {{:hdlq.zip|source}} codes for HDLQ. The paper describing the HDLQ code is {{:hdlq.pdf|here}}.